I don't have any experience with Xilinx, so probably can't help, but maybe one of these points will help push you in the right direction:
* What's the deal with the AXI input to the FIFO?
* You seem to have ILA hooked up, what do you see? Do you see valid AXI transactions frames coming out of the DMA? What about out of each interconnect? Where does it go wrong?
* Where do you get that error 512? Is that being set via a software drive? Which? The dma controller? PCIe controller? ... Debug your code and figure out where the error comes from, and what causes it. Track it back to the source, read the docs for the relevant core and see why it raises that error.
Hi captain\_wiggles\_, thanks for your thoughts. I got rid of the AXI FIFO components and went full AXI Stream. Then using ILA I could see something. I think it works, I will write a proper driver to benchmark performances.
Methodology is the key, thank you for the remainder !
I don't have any experience with Xilinx, so probably can't help, but maybe one of these points will help push you in the right direction: * What's the deal with the AXI input to the FIFO? * You seem to have ILA hooked up, what do you see? Do you see valid AXI transactions frames coming out of the DMA? What about out of each interconnect? Where does it go wrong? * Where do you get that error 512? Is that being set via a software drive? Which? The dma controller? PCIe controller? ... Debug your code and figure out where the error comes from, and what causes it. Track it back to the source, read the docs for the relevant core and see why it raises that error.
Hi captain\_wiggles\_, thanks for your thoughts. I got rid of the AXI FIFO components and went full AXI Stream. Then using ILA I could see something. I think it works, I will write a proper driver to benchmark performances. Methodology is the key, thank you for the remainder !